This invention relates to MOS imagers, and more particularly relates to techniques for increasing the dynamic range of a MOS imager.
Conventionally, MOS imagers are characterized by a linear voltage-to-light response, or transfer function; that is, the imager output voltage is approximately linearly related to light incident on the imager. Specifically, the output voltage transfer function is linearly proportional to the intensity of the light incident on the imager. This linear transfer function can be characterized by a dynamic range, given as the ratio of the highest detectable illumination intensity of the imager to the lowest detectable illumination intensity of the imager. It is well understood that the dynamic range of the transfer function sets the overall dynamic range of the imager. If the dynamic range of a scene exceeds the dynamic range of an imager, portions of the scene will saturate the imager and appear either completely black or completely white. This can be problematic for imaging large dynamic range scenes, such as outdoor scenes.
Conventionally, a MOS imager pixel includes a phototransistor or photodiode as a light detecting element. In operation, e.g., the pixel photodiode is first reset with a reset voltage that places an electronic charge across the capacitance associated with the diode. Electronic charge produced by the photodiode when exposed to illumination then causes charge of the diode capacitance to dissipate in proportion to the incident illumination intensity. At the end of an exposure period, the change in diode capacitance charge is detected and the photodiode is reset. The amount of light detected by the photodiode is computed as the difference between the reset voltage and the voltage corresponding to the final capacitance charge. The illumination intensity that causes the photodiode capacitance charge to be completely dissipated prior to the end of the exposure period, thereby saturating the pixel, sets the upper end of the pixel dynamic range, while thermally generated photodiode charge and other noise factors set the lower end of the pixel dynamic range.
A variety of techniques have been proposed for expanding the dynamic range of a MOS imager. In one particularly effective technique, the voltage-to-light transfer function of the imager is modified to be a nonlinear function of illumination intensity, with transfer function slope increasing linearly as a function of illumination intensity. This transfer function modification is typically implemented as a photodiode capacitance charge control function within a CMOS imager pixel.
Specifically, in this technique, over the course of an exposure period a control voltage is applied to the photodiode capacitance to control charge dissipation from the capacitance. The charge control voltage is typically decreased from the starting pixel reset voltage value to, e.g., electrical ground, with each control voltage value at a given time during the exposure period setting the maximum charge dissipation of the photodiode. This control voltage decrease acts to increase the photodiode charge dissipation capability, whereby the pixel can accommodate a higher illumination intensity before saturating, and the dynamic range of the pixel is thusly increased. This charge dissipation control overrides the conventional linear voltage-to-charge transfer function of the pixel to produce a nonlinear transfer function, generally referred to as a compressed transfer function, and a correspondingly expanded dynamic range of the pixel and the imager.
Theoretically, the charge dissipation control voltage applied to a pixel photodiode is preferably continuously adjusted over the course of an exposure period. This enables the production of almost any desired transfer function compression characteristic. For many applications, this theoretical condition is not practical, however. Conventional MOS imagers include an array of pixel columns and rows and typically do not include pixel memory. Therefore, at the end of an exposure period each row of pixel values must be immediately read out. But in general, only one row of pixel values can be read out at a time. To accommodate this condition, the exposure periods of the pixel rows are typically staggered in a time sequence corresponding to the sequential pixel row read out. As a result, the desired pixel charge control voltage waveform must also be applied to the pixel rows in a staggered sequence; the same control voltage waveform is applied to every pixel row but is staggered in time between rows.
As a practical matter, given, e.g., a conventional VGA imager including 480 pixel rows, it would be difficult to deliver 480 continuous-time control voltage waveforms to the imager array or to generate 480 delayed versions of a single continuous-time waveform. It has been found that the approximation of a continuous-time control voltage waveform by a discrete-time, or stepped, control voltage waveform addresses this timing concern while enabling more flexibility and ease in control voltage generation and sequential delivery to a pixel array. In this technique, a desired continuous-time control voltage waveform, or transfer function compression curve, is approximated by voltage steps. This results in a finite number, e.g., eight, of distinct control voltage levels to be applied in a discrete manner to a pixel over the course of that pixel""s exposure period. Conventionally, the prescribed discrete-time analog control voltages are generated off-chip from the imager array and then delivered to each pixel row on-chip in a staggered sequence controlled by, e.g., a digital controller. It has been found that this scenario enables good pixel control as well as timing control and additionally provides the ability to modify the transfer function compression characteristic.
It has been recognized that the discrete analog voltages produced to impose imager transfer function control preferably are regulated to be precise and noise free, and preferably are maintained free of glitches, where a xe2x80x9cglitchxe2x80x9d is here defined as a rapid excursion, or spike, in the voltage. Without such regulation, the desired compression function could be distorted, with the resulting images including noise or appearing unnatural. Regulation of the control voltages is particularly important as the voltages are switched from one pixel row to the next. Specifically, when a given control voltage is applied from one pixel row to the next, a voltage excursion, or glitch, is produced due to an inherent row switching capacitance. Such an excursion in a voltage source could cause rows of pixels already connected to that voltage to dissipate charge or accumulate charge in a manner not consistent with the desired transfer function.
For this reason, conventional imager configurations typically employ external, off-chip analog control voltage sources having output voltages that are bypassed by large and external bypass capacitors. The bypass capacitors are employed to eliminate glitches due to row switching capacitance as the charge control voltages are sequentially applied to rows of an imager. It has been understood that without the use of such bypass capacitors, a staggered-row control voltage application scenario does meet most imager performance requirements.
The typical row capacitance of a VGA imager is on the order of about 5 pF. In order to effectively reduce switching glitches from this row capacitance by an order of magnitude or more, bypass capacitors for each analog control voltage source are required to each be at least about 50 pF, and more typically are provided as an external capacitor or about 0.1 xcexcF for each external analog voltage generation circuit. This external control voltage generation circuit configuration adds to imager system power consumption, complexity, cost, and overall imager system extent, and influences other imager performance factors. But practical implementation of a compressive MOS imager transfer function characteristic has heretofore required accommodation of the bypass capacitor configuration and the limitations imposed by this configuration.
The invention provides the ability to effectively and precisely implement a desired imager and pixel transfer function, to expand imager dynamic range, in a manner that is immune to capacitances of the imager. This is accomplished in accordance with the invention with an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, the circuit having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and connected to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels. The application by the switch circuit of each of the charge control voltages to a row of pixel reset nodes is characterized by a voltage application settling time, tS, that is less than about 1/Nrf, where N is an integer and f is imager frame rate.
This configuration causes the voltage spikes, or glitches, associated with the imager row capacitance, to decay substantially completely during the time over which an imager pixel row is accessed to apply a control voltage. As a result, the voltage spikes have no impact when a sequence of control voltages is applied to rows of an imager, e.g., when the switch circuit is configured to apply the voltages through the imager pixel rows sequentially. No bypass capacitors are therefore required, and the charge control voltage generation circuit can be fabricated quite compactly, preferably monolithically with the imager pixel array and switching circuit, e.g., in a CMOS fabrication process. Here all of the voltage generation and switch circuit elements can be fabricated in-line with the imager, e.g., with the switch circuit provided as MOS transistor switches.
In accordance with the invention, for applications in which charge control voltage application to pixel reset nodes is to be carried out across an imager array simultaneously, rather than row-by-row, the voltage spikes, or glitches, associated with the control voltages can be caused to decay substantially completely without impacting imager performance by requiring that the voltage application settling time, tS, be less than about the duration specified for each of the control voltages in the plurality of control voltages.
The invention provides for embodiments in which the light detecting element of MOS imager pixels can be provided as, e.g., a photodiode, a phototransistor, or other suitable configuration. The reset node of the imager pixels can be provided as a MOS reset transistor. The sense node of the imager pixels is preferably connected to the light detecting element at a node corresponding to capacitance of the light detecting element.
In accordance with the invention, the charge control voltage application settling time, tS, can be specified as tS=RthC, where Rth is a Thevenin resistance of the charge control voltage generation circuit topology and C is an effective capacitance of the pixel array. To meet the requirement of the invention for causing voltage spikes to decay sufficiently rapidly, the Thevenin resistance, Rth, of the charge control voltage generation circuit topology, is preferably less than 1/NrfC, where Nxe2x89xa72.
The invention provides embodiments wherein the charge control voltage generation circuit topology includes a plurality of resistors, which in one preferable example are connected in series between two voltages. The resistors can be provided as monolithically fabricated polysilicon resistors for applications in which integration of the entire imager system is preferred. A voltage source and/or a current source can be included with the resistor network, and each can be provided as variable sources; it can be preferred to provide the current source as a transistor current source. In a topology including a series connection of resistors, the series can be connected between, e.g., a power supply voltage and electrical ground. Here a current source can be connected between one of the plurality of resistors and the power supply voltage or electrical ground. In other embodiments, the invention provides for a charge control voltage generation circuit topology that includes a digital register for each charge control voltage in the plurality of voltages, or that includes a sample-and-hold amplifier for each charge control voltage in the plurality of voltages.
It can be preferred for many applications to provide a charge control voltage generation circuit configuration such that at least one of the voltages produced by the circuit is a variable voltage. In one embodiment, each of the charge control voltages is a substantially constant voltage level. The plurality of voltages here produce a stepped sequence of voltage levels. Alternatively, the plurality of charge control voltages can together produce a substantially continuously-changing voltage level. For MOS photodiode-based imagers, it can be preferred to provide a stepped sequence of decreasing control voltage levels to increase the dynamic range of the imager. Imager dynamic range can particularly be increased by selecting the plurality of control voltage levels to impose a nonlinear transfer function on the imager pixels.
The imager system of the invention and the corresponding charge control voltage generation and application techniques enable a very efficient and elegantly non-complex imager system design and operation. By eliminating the need for large bypass capacitors, the system of the invention can be compactly fabricated, e.g., as a single monolithically-integrated system. This high degree of integration enables the use of the imaging system in a wide range of consumer and specialty photography, surveillance, robotic control, and other applications for which high performance, low cost, efficiency, and size are all preferred.